In recent years, the dimensions of MISFETs (metal insulator semiconductor field effect transistors), and in particular the gate electrode thereof, has been decreasing. This dimensional reduction in the MISFET has been performed in accordance with the scaling law, but various problems have appeared as dimensions are reduced. It has therefore become difficult to satisfy both the suppression of the short channel effect of the MISFET while at the same time securing a high current driving power. Accordingly, much research and development has been conducted in recent year regarding devices that have novel structures, that is, structures other than the conventional planar type (flat type) of MISFET.
The FinFET is one of the above-described devices having a novel structure. It is a three-dimensional MISFET different from the planar type MISFET. The FinFET has a “fin” formed by processing a semiconductor layer. This fin is a region in a thin strip form (in the form of a rectangular solid) and both side-surface portions of the fin are used as channels of the FinFET. The gate electrode of the FinFET is formed over both side surface portions of the fin so as to straddle over the fin. It therefore has a so-called “double-gate” structure. The configuration of the FinFET structure is superior to the conventional planar MISFET, which has a single gate structure, from the standpoint of potential control of the channel region by the gate electrode. The FinFET has therefore advantages such as high punch-through resistance between a source region and a drain region, as well as suppression of a short-channel effects even at a smaller gate lengths. Because the FinFET uses the both side surface portions of the fin as a channel, an area of the channel region through which a current is caused to flow can be made greater, and a higher current driving power can be attained.
It has been discovered, however, that it can be difficult to control the threshold voltage of the FinFET. For example, in the conventional planar type MISFET, the threshold voltage is controlled by adjusting the impurity concentration in the channel region. In this case, as the planar type MISFET becomes smaller, the concentration of an impurity to be introduced into the channel region becomes higher in accordance with the scaling law. This means that in the conventional planar type MISFET, size reduction decreases the distance between the source region and the drain region, tending to cause punch-through. The punch-through is therefore controlled by raising the impurity concentration of the channel formed between the source and the drain. An increase in the impurity concentration of the channel however increases the variation in the impurity concentration among elements, resulting in an increase in the variation in the characteristics of the planar type MISFET. In addition, it enhances impurity scattering due to carriers passing through the channel, causing deterioration in the mobility of the carriers.
On the other hand, the FinFET is based on an operating principle similar to that of a fully-depleted MISFET so that the impurity concentration in the channel can be reduced. As such, the FinFET structure is capable of reducing the variation in electrical characteristics among MISFETs due to a high impurity concentration. More specifically, in a FinFET structure, the threshold voltage is controlled not by adjusting the concentration of an impurity to be introduced into the channel, but by selecting an appropriate workfunction of the gate electrode. In the FinFET, once a material of the gate electrode is determined, so too is the threshold voltage. Thus, it is difficult to cover the large range of threshold voltages in current FinFET structures that are needed for more advanced integrated circuit designs.
Accordingly, it is desirable to provide improved FinFET structures, and methods for fabricating the same, that provide for a greater range of threshold voltages. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.